DATA-COMPRESSION TECHNIQUES CAN HELP MANAGE THE ESCALATING COST OF TEST IN NANOMETER DESIGNS.

The test time that scan tests require typically dominates manufacturing-test costs for digital designs.The increase in design complexity and the requirements for delay tests have made test time a design parameter that requires active management in nanometer designs. As the number of patterns increases, it takes more tester-buffer space to hold the complete test set, and it takes longer to execute the test set in manufacturing.

To address both the data-volume and test-time problems,test engineers and test architects have developed techniques
employing on-chip hardware that compresses the test-stimulus and response patterns and then applies them to the chip under test. Luckily, there are many test architectures that engineers can employ for test-data compression.

Compression-methods background

The dominant method of testing digital circuits is the use of an ATPG (automatic test-pattern generator) to target a stuckat
or transition fault model at all of the circuit nodes. In circuits that contain storage elements, engineers can use scan registers to enable control and observation of the storage elements and ensure high fault coverage. When the ATPG generates too many test patterns, the test-application time becomes too long, and engineers must use on-chip-compression techniques to minimize test time and, thus, test costs.

Test compression builds on technology originally developed for LBIST (logic built-in self-test). Figure 1 shows the general
structure of compression logic within a chip or core. The system decompresses a compressed input stream and feeds it into the internal scan chains, some of which may be inside cores within the design. The system optionally feeds the output from the internal scan chains through masking logic and then compresses it into an output stream. Engineers can use several architectures for the input decompressor and the output compressor.

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