On-chip Compression
作者:Brion Keller   发布时间:2007-04-11 14:50:47   浏览次数:780

Interoperability requirements

Typically, vendors insert compression architectures at the RTL or gate level, and the ATPG and diagnostics engines need to understand the architecture of the compression to generate and diagnose tests with these structures on-chip....

 

References
  1. Accellera Open Compression Initiative, www.accellera.org/activities/oci-tc/.
  2. Barnhart C, et al, "Extending OPMISR beyond 10X Scan Test Efficiency," IEEE Design & Test of Computers, September to October 2002.
  3. Rajski, J, et al, "Embedded Deterministic Test for Low Cost Manufacturing Test," Procedures of the International Test Conference, pg 301, 2002.
  4. Samaranayake, S, E Gizdarski, N Sitchinava, F Neuveux, R Kapur, and T Williams, "A Reconfigurable Shared Scan-in Architecture," Procedures of the VLSI Test Symposium, pg 9, 2003.
  5. Koenemann, B, C Barnhart, B Keller, T Snethen, O Farnsworth, D Wheater, "A SmartBIST Variant with Guaranteed Encoding," Procedures of the Asian Test Symposium, pg 325, 2001.
  6. Mitra, S, KS Kim, "X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction," Procedures of the International Test Conference, pg 311, 2002.
  7. Wohl, P, J Waicucauski, and S Patel, "Scalable Selector Architecture for X-Tolerant Deterministic BIST," Procedures of the Design Automation Conference 2004, pg 934.

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